In some double-data rate (DDR) memory systems, command busses are trained using a link training procedure on power-on of the system to align the command slots targeting specific memory channels. Training a link may refer to aligning signals in the link between system memory and a memory controller, or a processor including memory control logic, to as close to optimal positions as possible.
After power-on of the system, a system reference clock, usually provided by a common clock source (e.g., an oscillator mounted on the system level board), may start toggling. This system reference clock may be provided to the processor and a memory buffer between the processor and the system memory for use a reference clock. This reference clock may be used for generating internal clocks such as, for example, internal memory buffer clocks and clocks to one or more memory modules. Although this reference clock may be suitable for many applications, the frequency of the reference clock may be relatively slow, which sometimes leads to clock jitter and long-term drift for internally-generated clocks.
all in accordance with embodiments of the present disclosure.